1. Field of the Invention
The present invention relates to a resynchronization circuit used for transferring data between circuits which use clock signals of the same frequency but different phases, wherein data which is in synchronization with one of the clock signals is resynchronized with the other clock signal, and the resynchronized data is output from the resynchronization circuit.
2. Description of the Prior Art
For example, a system LSI circuit for controlling read and write operations of a memory has a resynchronization circuit for achieving transfer of data which is output from the memory in synchronization with a reception-side clock signal to a circuit which operates in synchronization with a system clock signal having the same frequency as that of the reception-side clock signal but a different phase from that of the reception-side clock signal in the process of controlling a read operation. Specifically, the resynchronization circuit resynchronizes the data with the system clock signal (i.e., allows the data to migrate to the system clock signal) to output the resynchronized data.
An example of such a synchronization circuit is disclosed in Japanese National Phase PCT Laid-Open Publication No. 2001-520417. The synchronization circuit disclosed in this publication includes a flip flop for holding received data at a rising edge of a system clock signal and a flip flop for holding the received data at a falling edge of the system clock signal. The output of any one of the flip flops is selected according to the phase difference between a reception-side clock signal and the system clock signal, and the selected output is held in synchronization with the system clock and then output from the synchronization circuit.
With such a structure, data which is in synchronization with the reception-side clock signal can be resynchronized with the system clock signal.
However, since the conventional resynchronization circuit is designed such that received data is held at a rising or falling edge of the system clock signal, the data can be held at a timing away from the center of a period during which the data is effectively output. Thus, as the speed of the reception-side clock signal, or the like, increases (i.e., as the frequency of the reception-side clock signal, or the like, increases), latching of the data becomes more difficult (i.e., the migration margin decreases), and accordingly, it becomes more difficult to increase the speed of data transfer.